Change the Modelsim directory to the unzipped folderĥ. Note that you should create your reconfiguration controller and AVMM read/write controller as these controls are done in test bench in the example.Ģ. The Qsys source files of the IPs used for HDL generation is in the source folder of the zip. ![]() The design also come with example test bench and TCL file to run simulation in Modelsim for reference. The example will demonstrate dynamic reconfiguration of one channel a time as well as broadcast mode where two channels are reconfigured at the same time. The design consist of two transceiver channels with fixed data pattern. The purpose of this design example is to assist users to have quick start with the Arria 10 transceiver dynamic reconfiguration with embedded streamer and multiple profile. ![]() This basic design example with Modelsim simulation demonstrates the implementing of Arria 10 Native PHY dynamic reconfiguration with embedded streamer and standard PCS. ![]() Arria 10 Native PHY dynamic reconfiguration with embedded streamer and standard PCS design example Overview
0 Comments
Leave a Reply. |
Details
AuthorWrite something about yourself. No need to be fancy, just an overview. ArchivesCategories |